More and more transistors are integrated in a single chip as the complexity of a circuit design growing, it not only increases the execution time of a scan test for a chip but also its test cost. Therefore, a serialized compressed scan architecture (SCSA) with a lot of scan chains but limited test inputs and outputs has been widely used in an integrated circuit (IC) as a design-for-testability (DFT) feature. By increasing the number of scan chains of a circuit, the scan chain length is decreased, which causes the testing time decreased. A test data compressed circuit is further used to reduce test data volume, so as to decrease the test cost. However, since a circuit design complied with a standard test interface has been widely implemented for test integration of an IC, it is difficult to directly implement the test integration of the ICs for the SCSA of a non-standard test interface.